Northrop Grumman’s Defense Systems has an opening for a Staff FPGA (DSP) Digital Design Engineer with an active clearance, to join our team of qualified, diverse individuals. This position will be in Northridge, CA. This position is 100% on site with no remote opportunities.
The Staff FPGA (DSP) Digital Design Engineer reports to the Chief Engineer and is responsible for leading multiple software teams for development activities.
As an integral part of our multi-discipline engineering team in Advanced Weapons, you will be on the forefront of developing next generation solutions to protect technology for our nation’s warfighters. The ideal candidate will be supporting one of our programs for defining and architecting a secured missile weapon system. This position will require close collaboration with team members of other projects within the organization for security architecture designs as well as external partners and customers.
Responsible for research, design, and development for complex high speed digital designs.
Support the implementation of digital FPGA hardware architecture and algorithms.
Collaborate with Systems Engineering to ensure firmware design meets system level requirements, review designs and analysis.
Basic Qualifications for Staff FPGA (DSP) Digital Design Engineer:
Bachelor’s degree in electrical engineering or other STEM (Science, Technology, Engineering or Mathematics) discipline with 12 years of digital verification engineering experience using industry standard simulation tools; 10 years with an MS degree; 8 years with PhD.
Must have hands on FPGA design experience with VHDL and/or Verilog within the past 3 years.
Proficient in DSP algorithms and its implementation onto the FPGA using MATLAB and SimuLink.
Experience with AMD/Xilinx and/or Intel/Altera SoC FPGAs.
Experience with Electronic Design Automation (EDA) Tools: Vivado, Quartus, and QuestaSim.
*Must have an active DoD Secret Clearance to start with the ability to get SAP.
Preferred Qualifications for Staff Engineer Digital:
Expertise in high-speed FPGA implementation such as AXI, DMA, PCIe, HSSI, DDR3, Ethernet, etc.
Strong design skills in VHDL & Verilog.
Experience in FPGA physical constraints and achieving timing closure.
Experience in developing low-level FPGA requirements and developing verification procedures.
Background in RF design is a plus.
Experience with board or system level debug using test equipment such as oscilloscopes, logic and spectrum analyzers, RF signal generator, etc.
Generation of complex test benches in Modelsim or Questasim to support formal Verification.
Familiarity with the VxWorks RTOS, its architecture and development tools is a plus.