Cadence

Lead Design Engineer

SHANGHAI Full time

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

  • Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies.

Specific duties include:

  • Proficiency in logic design, simulation
  • Proficiency in Verilog and its simulation environment
  • Good knowledge of IC design
  • At least seven year experience working on digital IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

Position Requirements:

  • Essential Qualifications: Must have BS degree with 6~10+ years of applicable experience, MS degree with 3~7+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
  • Essential that the individual demonstrates strong communication, verbal and written.

Requires good communication skills in English.

  • Will have demonstrated successful completion of 10+ design projects as an individual contributor
  • Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience

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