Job Details:
Job Description:
The Custom SoC team develops next-generation Xeon-based solutions tailored for server, AI, and data center applications. In this role, you will collaborate with leading customers on high-visibility programs that shape the future of computing. You’ll join a world-class engineering team leveraging advanced design methodologies and cutting-edge process technologies to deliver industry-defining products.
The role’s responsibilities include but are not limited to:
- Develops the logic design, register transfer level (RTL) coding, simulation, and provides DFT timing closure support as well as test content generation and delivery to manufacturing for various DFx content (including SCAN, MBIST, and BSCAN).
- Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC under DFT being designed (including TAP, SCAN, MBIST, BSCAN, proc monitors, in system test/BIST).
- Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
- Applies various strategies, tools, and methods to write and generate RTL and structural code to integrate DFT.
- Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
- Reviews the verification plan and drives verification of the DFT design to achieve desired architecture and microarchitecture specifications.
- Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
- Integrates DFT blocks into functional IP and SoC and supports SoC customers to ensure high-quality integration of the IP block.
- Collaborates with post silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
- Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.
Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
- Bachelor's degree in Computer or Electrical Engineering, or a related field with a year of related experience OR Master's degree in Computer or Electrical Engineering, or a related field
- 1year experience with test architecture
Preferred Qualifications:
- 6+ months experience with
- GLS to resolve stuck-at and at-speed test scenarios
- ATPG coverage analysis
- EDT configuration setup
- TCL, Python, Perl and/or C++ programming
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:
College Grad
Shift:
Shift 1 (United States of America)
Primary Location:
Virtual US
Additional Locations:
Business group:
At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US: $104,890.00-170,890.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 11/28/2025