Staff Engineer, Physical Design Engineering

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

          

Analog Devices’ Digital Business Unit (DBU) is seeking a Staff STA Engineer to lead timing sign-off and closure for complex mixed-signal SoCs manufactured on advanced process nodes and operating at high-speed clock rates. These SoCs integrate multiple processor cores and high-performance signal processing hardware. The role ensures that designs meet timing, signal integrity, and reliability requirements through advanced analysis and optimization techniques.

Key Responsibilities

• Perform full-chip and block-level STA for multiple modes and corners.
• Analyze and resolve setup, hold, and clock domain crossing (CDC) issues.
• Create and validate timing constraints (SDC) for synthesis and P&R flows.
• Execute timing sign-off using industry-standard tools (e.g., PrimeTime, Tempus).
• Implement ECOs for timing fixes and validate changes.
• Collaborate with RTL, physical design, and DFT teams to ensure timing requirements are met.
• Develop automation scripts (TCL, Python, Perl) to streamline STA tasks and improve efficiency.
• Address challenges related to OCV, AOCV, POCV, and multi-voltage domains.

Position Requirements

• Education: B.Tech/M.Tech in Electrical/Electronics Engineering.
• Experience: 9–12 years in STA and physical design implementation for high-speed SoCs on advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm).
• Strong expertise in Static Timing Analysis, constraint development, and sign-off.
• Ability to innovate flows to meet QoR targets and ensure predictability.
• Good understanding of device/interconnect and circuit aspects of UDSM technologies.
• Proficiency in TCL, Python, or other scripting languages.
• Excellent communication skills and ability to work in a cross-functional global team.
• Experience with low-power design techniques (UPF/CPF).
• Familiarity with signal integrity and power integrity analysis.
• Knowledge of advanced process nodes and variation modeling.

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For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

          

Required Travel: Yes, 10% of the time

          

Shift Type: 1st Shift/Days