We are seeking a highly skilled and hands-on Timing Doer to join our full-chip timing team. This role is critical to achieving top-level timing closure for complex SoC/ASIC designs. The ideal candidate is a technical expert in STA, scripting, and timing infrastructure, capable of driving timing accuracy, automation, and scalability across the full chip.
Key Responsibilities:
Full-Chip STA Execution: Run and maintain top-level timing analysis across all modes and corners using tools like Primetime. Timing Coverage and Quality: Ensure every path is timed correctly; track and improve timing quality metrics such as coverage, margin distribution, and skew. Tool and Environment Management: Maintain and update STA tool versions and patch releases. Seamlessly roll out PVT corner changes and scaling methods for unsupported libraries. Automation and Scripting: Develop robust scripts (Tcl, Python, shell) to automate STA runs, report generation, ECO flows, and environment setup. Create scalable and reusable infrastructure for timing tasks. Library and Corner Handling: Implement scaling techniques for missing libraries. Rapidly adjust PVT corners and integrate changes into the flow. Collaboration and Support: Work closely with timing owners and block teams to resolve cross-boundary timing issues. Provide infrastructure and tooling support to timing owners. Signoff Readiness: Ensure timing signoff criteria are met across all corners and modes. Validate timing post-ECO and post-layout. Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning. Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
This position is not eligible for Intel immigration sponsorship.
Minimum Qualifications:
Preferred Qualifications:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 02/20/2026