Senior/ Staff Chip Top Physical Design Engineer

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. 

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world’s largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities

• Execute SoC Top-level physical design and actively drive full-chip convergence
• Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
• Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
• Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
• Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

Basic Qualifications

• B.Sc. or M.Sc. in Electrical Engineering
• 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below)
• Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills
• Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)
• Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration

 

Preferred Qualifications

• Deep understanding of Power & Noise analysis (EM/IR)
• Experience with DFT (Design for Test) integration into the physical design flow
• Background in high-speed interfaces or data center protocols