Be part of Intel’s AI Group and help shape the silicon behind Intel’s most advanced AI platforms.
In this role, you will part of a team leading post-silicon validation of the latest, cutting-edge PCIe, HBM, and Die-to-Die (D2D/UCIe) technologies in complex AI SoCs. You will tackle the most challenging silicon issues, define and drive validation strategy, and work closely with architecture, design, firmware, and platform teams to deliver robust, high-performance, production-ready silicon.
Key Responsibilities :
Lead post-silicon validation for one of following domains in AI accelerators and SoCs: PCIe, HBM, UCIe.
Define validation strategy, coverage, and debug methodology across multiple high-speed interfaces.
Mentor and provide technical guidance to junior and mid-level validation engineers.
Execute pre-silicon and post-silicon validation, drive first power-on, bring-up, characterization, and production readiness activities.
Debug complex, system-level issues spanning protocol, firmware, electrical, and platform layers.
Develop and review validation tests, automation, and debug tools (primarily C/C++).
Collaborate with architecture, design, firmware and platform teams to influence design robustness and future architectures.
Represent validation in cross-functional reviews and silicon readiness milestones.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
8+ years of hands-on post-silicon validation experience in high-speed I/O and/or memory subsystems.
Strong expertise in one domain (PCIe, HBM, or UCIe).
Deep understanding of system-level bring-up, debug, and root-cause analysis on complex SoCs.
Extensive experience with validation and debug tools (protocol analyzers, exercisers, scopes, logic analyzers).
Proficiency in C/C++ for validation, automation, and debug development.
Strong understanding of SoC architecture.
Preferred Qualifications
Experience with PCIe Gen5/Gen6, advanced HBM generations, or UCIe-based designs.
Background in AI accelerators, GPUs, chiplets, or high-performance computing platforms.
Knowledge of signal integrity, electrical characterization, and high-speed interface bring-up.
Experience influencing silicon architecture or driving cross-team technical initiatives.
Strong understanding of Linux-based validation environments.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.