Senior Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.  Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day

Location: Hyderabad

BE/BTECH/ME/METCH or Equivalent Degree

Job role

Job responsibilities:

JOB description

Qualification: BE/BTECH/ME/MTCH

Exp:10-18 years Equivalent or relevant

He/she will be part of the Verification team verifying Ips/subsystems and SoCs leading to first Si success. Require a Strong hold on UVM/Test bench Development, System C Knowledge Prior Experience of at least 4-5 years in SoC verification at RTL/Netlist/Netlist+SDF level Required Experience in Power Aware Verification Worked at least 4 years in the PCIe Protocol Knowledge. Would be responsible Defining verification strategy, writing test plans, developing efficient test benches and test cases. Experience in Code coverage, Functional coverage and assertions are desired. ARM based SoC verification experience is an added advantage. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus

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