Principal VLSI Design Engineer, Sunnyvale, CA

Principal VLSI Design Engineer, Sunnyvale, CA

  

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Job Description:

Principal VLSI / ASIC Design Engineer (Networking ASICs)

Role Summary

You will architect, design, and implement complex networking ASICs. You will create chip‑level and block‑level architecture and micro‑architecture, write high‑quality RTL, and work closely with verification and physical design teams to deliver clean, efficient, and high‑performance silicon.

US Citizenship preferred

Location: Sunnyvale, CA

Onsite work required weekly 2 days per week; Tuesdays and Thursdays

Responsibilities

• Define ASIC architecture for networking chips, including data paths, packet processing, control logic, memory structures, and interfaces.
• Develop detailed micro‑architecture for complex blocks and ensure they meet functional and performance goals.
• Write clear, efficient, synthesizable RTL (SystemVerilog/Verilog) for the designed blocks. Create assertions and assist in functional coverage
• Work closely with verification engineers to ensure the RTL is fully tested, bug‑free, and meets all functional requirements.
• Provide guidance to the verification team on test plans, coverage goals, corner cases, and expected behavior.
• Collaborate with physical design engineers to ensure the design meets timing, area, and power targets.
• Review synthesis, timing, and power reports, and update RTL or micro‑architecture as needed.
• Participate in design reviews, provide clear feedback, and ensure compliance with design guidelines.
• Support integration and debug during simulation, emulation and silicon bring‑up.
• Identify technical risks early and propose simple, effective solutions.

Knowledge & Skills

• Strong understanding of ASIC architecture and micro‑architecture.
• Strong background in networking ASICs (switching, routing, packet processing, or similar preferred).
• Expert in RTL coding in Verilog or SystemVerilog, assertions and functional coverage
• Strong knowledge of digital design fundamentals, pipelining, clocking, resets, FIFOs, arbiters, and data path design.
• Experience working with verification teams and understanding of UVM‑based flows.
• Experience working with physical design teams and understanding constraints for timing, power, and area.
• Familiarity with EDA tools for simulation, synthesis, lint, CDC, timing analysis, and power analysis.
• Good written and verbal communication skills.
• History of technical contributions, innovation, or mentorship.

Required Experience

• Bachelor’s, Degree in Computer Science, Master’s, or PhD in Electrical Engineering, Computer Engineering, or similar.

#unitedstates

Accountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}

Health & Wellbeing

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

#unitedstates

#operations

Job:

Engineering

Job Level:

TCP_05

    

"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
– United States of America: Annual Salary USD 174,000 - 352,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered." "The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

   

No Fees Notice & Recruitment Fraud Disclaimer

 

It has come to HPE’s attention that there has been an increase in recruitment fraud whereby scammer impersonate HPE or HPE-authorized recruiting agencies and offer fake employment opportunities to candidates.  These scammers often seek to obtain personal information or money from candidates.

 

Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.  The credentials of any hiring agency that claims to be working with HPE for recruitment of talent should be verified by candidates and candidates shall be solely responsible to conduct such verification. Any candidate/individual who relies on the erroneous representations made by fraudulent employment agencies does so at their own risk, and HPE disclaims liability for any damages or claims that may result from any such communication.