By submitting your resume, you’re expressing interest in our 2026 RDSS (Research and Development Substitute Services) program. Please confirm your eligibility with the local district office before applying the role.
What you'll be doing:
Be part of an analog team building next generation NVLINK.
You will be responsible for the development and implementation of high speed interfaces, including TX/RX/Clocking/PLL.
Work closely with physical/layout engineers to floorplan and implement physical design of these functions.
Support debug, characterization and support product through high-volume production.
What we need to see:
MS / PhD in Electrical Engineering, Computer Engineering or related field with strong analog design background.
CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET); Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA)
You have interests in more than one of the following areas: digital links for display interfaces (such as HDMI, LVDS, DVI, MIPI PHY, Display Port), USB, low-jitter clock synthesis using PLL techniques, IO pads, high-speed serial links, and ADC.
Able to communicate in spoken and written English
Work effectively in a team, good communication skills, enthusiasm and positive energy.
Proficiency in scripting languages like perl, python, skill etc.
You are an expert with Cadence custom circuit design tools - particularly virtuoso
Experience running and debugging DRC and LVS with verification tools
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.