FPGA Design Engineer (Level 3 or 4)

RELOCATION ASSISTANCE: No relocation assistance available

CLEARANCE REQUIRED FOR START: No

CLEARANCE TYPE: Top Secret

TRAVEL: Yes, 10% of the Time

Description

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.

Join Northrop Grumman on our continued mission to push the boundaries of possible across space systems. Enjoy a culture where your voice is valued and start contributing to our team of passionate professionals providing real-life solutions to our world’s biggest challenges. We take pride in creating purposeful work and allowing our employees to grow and achieve their goals every day by Defining Possible. With our competitive pay and comprehensive benefits, we have the right opportunities to fit your life and launch your career today.

Northrop Grumman Space Systems, is currently seeking a Principal / Sr. Principal Digital Design Engineer for our Eastern Engineering team located in Linthicum, Maryland.

Roles and Responsibilities:

• Develop digital logic designs for space applications such as satellite command and control and sensor data processing

• Design, development, creation and modification of digital logic designs implemented with Xilinx and Microsemi FPGA IDEs

• Simulation and verification of FPGA logic designs, compliance requirements, and supporting validation at the system level

• Work with members of multi‐functional teams to develop innovative solutions

• Clear and effective communication to cross-functional team members 

• Documentation of design and analysis reports as well as test reports

Level 3 FPGA Design Engineer Basic Qualifications:

• (Level 3 education requirements) Bachelors in STEM discipline with 5 years of related experience, or a Master’s Degree with 3 years of related experience, or a PhD with 0 years of related experience

• Experience designing, architecting, and using various FPGAs in processor designs (knowledge of VHDL or other high level language a plus)

• Experience defining and executing development test plans and/or methods

• Must be a U.S. citizen

• No clearance required to start, but must have the ability to obtain and maintain a DoD Top Secret Clearance

Level 4 FPGA Design Engineer Basic Qualifications:

• (Level 4 education requirements) Bachelors in STEM discipline with 8 years of related experience, or a Master’s Degree with 6 years of related experience, or a PhD with 3 years of related experience

• Digital subsystem, ASIC, FPGA and/or digital board development experience and knowledge essential

• Candidate must have good communication skills, strong interpersonal skills, and good oral and written presentation skills

• Must be able to mentor and coach early career Engineers as needed

• Must be U.S Citizen

• Must be able to obtain and maintain Secret or Top-Secret level security clearance, per business requirements

Preferred Skills:

• Active DoD Top Secret Clearance

• Experience translating customer requirements into functional block diagrams that can be realized as FPGAs or other Digital Logic Circuit Card Assemblies

• Strong experience with Matlab and Simulink modeling and programming

• Develops detailed specifications from high level design goals and performs analysis of the hardware, system environment and design goals to enable selection and implementation of the desired system topology

• Can clearly present assigned work at program technical reviews, proposals, or other technical meetings

• Possesses strong interpersonal skills to work effectively within a development team to understand system level inter-dependencies and design constraints

• Conduct trade studies, identify and present alternate design options

• Experience with Systems Engineering principles

Primary Level Salary Range: $119,600.00 - $179,400.00

Secondary Level Salary Range: $149,300.00 - $223,900.00

The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.

Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.

The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.

Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.