We're looking for motivated and talented engineers to join the Performance Core CPU verification team.
You will join the team responsible for exhaustively verifying the architecture and micro-architecture changes implemented in the CPU using a combination of dynamic and formal verification methods.
Your responsibilities may include, but are not limited to, the following:
1. Technical ownership of formal verification of a microarchitecture block, methodology, or otherwise significant aspect of the P-Core CPU.
2. Understand and contribute to micro-architecture specification and define the formal verification strategy for a significant portion of the design.
3. Lead ROI analysis and recommend appropriate use of formal verification vs dynamic validation techniques for relevant parts of the CPU.
4. Document formal test plans and drive technical reviews of plans and proofs with design and architecture teams.
5. Post-silicon failure debug and sighting resolution.
6. Mentor junior team members.
7. Develop validation automation tools to accelerate execution.
8. Collaborate on validation approach and strategy beyond immediate team.
9. Work with global Formal verification experts and design teams within the organization.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Qualifications:
Candidate must have a Bachelors degree in Computer/Electrical Engineering or Computer Science and 3+ years of relevant work experience - OR - a Masters degree in Computer/Electrical Engineering or Computer Science and 2+ years of relevant work experience - OR - a PhD in Computer/Electrical Engineering or Computer Science with an emphasis on formal verification and 1+ years of relevant work experience.
1+ years of experience in/with:
1. Computer architecture with emphasis on out of order processor execution, memory hierarchy, and memory management.
2. Industry standard formal verification tools such as JasperGold, IFV, Questa Formal, VC Formal.
3. Hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools.
4. Assertion writing, checker development, coverage analysis, failure debug, root cause analysis.
5. Programming in at least one language: C/C++, Java, Specman E, OVM, UVM and familiarity with any of scripting languages: Perl, Python, Ruby, TCL.
Preferred Qualifications:
1. Knowledge of Intel Architecture ISA and system architecture, x86 assembly language.
2. Experience with pre- and post-silicon debug and analysis.
3. Research publications, patent filings, or other evidence of personal technical innovation in validation methodology advancement.
4. Applying sequential equivalence checking in complex micro-architectures.
5. Formal abstractions and other complexity reduction techniques.
6. Intel or industry pre-silicon verification of CPU cores, including specific areas of technical ownership/expertise relevant to CPUs.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.