Location: Neuchâtel, Switzerland.
At Semtech Corporation, our Wireless Analog/Digital and LoRa System teams in Neuchâtel and Grenoble are recognised globally for pioneering Low Power Wide Area Network (LPWAN) innovation.
Our expertise spans antenna design, analog and digital IC development, ultra-low-power systems, wireless protocols, and cloud-connected IoT solutions.
You will join a highly collaborative R&D environment helping to shape the next generation of LoRa and LoRaWAN system architecture — from silicon implementation through to real-world validation.
The Analog Laboratory and Layout Engineer plays a dual-role at the intersection of silicon characterization and IC layout implementation.
This position is responsible for developing advanced bench infrastructure, automated measurement solutions, and detailed performance analysis for CMOS IC designs operating from sub-GHz to 2.4 GHz.
Alongside laboratory characterization, you will contribute directly to IC layout design and verification during the chip development phase, ensuring designs are not only robust in theory, but measurable, testable, and optimized in practice.
At Semtech Corporation, we believe innovation starts with people. We are committed to empowering professional development through mentorship, continuous learning resources, and a collaborative, idea-rich engineering environment.
Our pay-for-performance culture rewards initiative, encourages growth, and recognises meaningful technical and leadership contributions. Engineers in this role are supported to broaden their influence, deepen their expertise, and actively shape both their own career progression and the future of our digital engineering capabilities.
The intent of this job description is to describe the major duties and responsibilities performed by individuals in this role. Additional job-related tasks may be assigned as needed.
All listed duties and responsibilities are considered essential job functions and requirements.