System Validation Engineer (NCG 2026)

Astera Labs is a rapidly growing semiconductor company that’s redefining connectivity for AI and cloud infrastructure. Our intelligent connectivity solutions—built on PCIe®, CXL™, Ethernet, and custom fabrics—enable seamless data movement across compute, memory, and storage. As part of our team, you’ll help validate the silicon that powers the world’s most advanced AI platforms.

Role Overview:

Validate high-speed interconnects and AI fabrics in custom silicon. Work on chip bring-up and debug for technologies like PCIe Gen5/Gen6, CXL, and memory-semantic fabrics.

Skills:

• Exposure to post-silicon validation or bring-up of connectivity IP blocks
• Knowledge of signal integrity analysis and eye diagram interpretation
• Familiarity with Linux systems, shell scripting, and version control (Git)
• Understanding of AI workloads and how interconnect bandwidth impacts performance
• Experience with memory coherency protocols and cache hierarchies

Key Responsibilities

• Execute post-silicon validation test plans for our Ethernet product line
• Use lab equipment (oscilloscopes, protocol analyzers, BERTs) to validate signal integrity and protocol compliance
• Develop and debug test automation scripts in Python, C/C++, or TCL
• Analyze performance, latency, and error recovery across AI connectivity fabrics
• Collaborate with design, firmware, and systems teams to root-cause issues and optimize performance
• Document validation results and contribute to debug guides and bring-up documentation

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• Solid understanding of digital logic, computer architecture, and high-speed serial protocols
• Familiarity with PCIe®, CXL™, or Ethernet standards
• Experience with scripting languages (Python, TCL) and basic programming (C/C++) and JMP
• Comfortable working with lab tools and debugging hardware
• Strong analytical and communication skills

Preferred Skills

• Exposure to post-silicon validation or bring-up of connectivity IP blocks
• Knowledge of signal integrity analysis and eye diagram interpretation
• Familiarity with Linux systems, shell scripting, and version control (Git)
• Understanding of AI workloads and how interconnect bandwidth impacts performance
• Experience with memory coherency protocols and cache hierarchies

What You’ll Gain

• Hands-on experience with industry-leading connectivity solutions for AI infrastructure
• Mentorship from engineers at the forefront of silicon innovation
• Exposure to the full lifecycle of chip development—from tape-out to deployment
• Opportunity to contribute to products used by top hyperscalers and cloud providers

The base salary range for this role is $130,000 - $150,000 annually.