Staff Engineer, Physical Design Engineering

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

          

Analog Devices’ Digital Business Unit (DBU) is seeking a Senior Physical Design Engineer to lead the development of complex mixed-signal SoCs manufactured on leading-edge process nodes and operating at high-speed clock rates. These SoCs integrate multiple processor cores and high-performance signal processing hardware. The role involves end-to-end physical implementation of ASIC/SoC designs, ensuring optimal performance, power, and area (PPA) while meeting timing and manufacturability requirements.

Key Responsibilities

• Execute RTL-to-GDSII flow including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
• Perform Static Timing Analysis (STA), power integrity checks, signal integrity (SI), and electromigration (EM) analysis.
• Optimize PPA metrics through congestion analysis, routing strategies, and library utilization.
• Ensure DRC/LVS compliance, run physical verification, and manage ECOs for design revisions.
• Collaborate with RTL, DFT, packaging, and backend teams for seamless integration.
• Customize design flows, automate processes using TCL, Python, Perl, and contribute to CAD development.
• Implement designs on advanced process technologies (e.g., 22nm, 16nm, 5nm, 3nm).
• Mentor junior engineers and contribute to methodology improvements.
• Experience with low-power design techniques (UPF/CPF).

Position Requirements

• Education: B.Tech/M.Tech in Electrical/Electronics Engineering.
• Experience: 9–12 years in physical design implementation of complex high-speed SoCs on advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm).
• Expertise in floorplanning, power planning, placement & routing, clock planning, CTS, and parasitic extraction.
• Strong knowledge of Static Timing Analysis, constraint development, and sign-off.
• Ability to innovate flows to meet QoR targets and ensure predictability.
• Good understanding of device/interconnect and circuit aspects of UDSM technologies.
• Proficiency in TCL, Python, or other scripting languages.
• Excellent communication skills and ability to work in a cross-functional global team.

#LI-SM1

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

          

Required Travel: Yes, 10% of the time

          

Shift Type: 1st Shift/Days