About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
As a Digital IC Design Senior Principal Engineer at Marvell, you will be part of the Central Engineering business group. If Marvell is viewed as a wheel, Central Engineering serves as the central hub, delivering critical IP and architecture capabilities leveraged across multiple business units, including Networking, Automotive, Storage, and Security.
In this role, you will focus on the development of UALink-related switch designs, contributing to high-performance, scalable interconnect solutions used in cutting-edge silicon products. You will work closely with a small, highly experienced digital design team to architect, implement, and optimize complex switch logic that enables efficient, low-latency communication in advanced systems.
This team tackles some of the most challenging design problems in the industry and plays a critical role in Marvell’s technology roadmap. The IP developed by this group is widely adopted across Marvell and by external customers, including leading chip companies and well-known global technology firms.
What You Can Expect
- Design, develop, implement, verify, and document micro-architecture and RTL for complex power management integrated circuits.
- Work closely with system and chip architects to design industrial quality implementations.
- Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs.
- Produce comprehensive block uArchitecture and register Specs.
- Schedule detailed reviews with cross-functional teams Evaluate and participate in improving design and verification methodologies.
- Supervise or mentor other digital design engineers.
What We're Looking For
- Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 15+ years of relevant industry experience; or Master’s degree with 10–12 years of experience; or PhD with 8–10 years of experience.
- Strong experience in defining micro-architecture specifications based on industry standards and system-level architectural requirements, particularly for high-speed interconnects, switch fabrics, or scalable on-chip/off-chip communication systems.
- Proven expertise in SystemVerilog RTL design, including implementation of complex control and data-path logic.
- Experience creating scalable, modular, and reusable RTL design components for large, multi-block systems.
- Strong understanding of switch design concepts, packet- or transaction-based data movement, and performance/latency trade-offs.
- Familiarity with synthesis and static timing analysis (STA), including timing closure considerations for high-performance designs.
- Experience collaborating across RTL design, synthesis, and implementation flows to ensure timing, performance, and quality-of-results (QoR) targets are met.
- Familiarity with embedded micro-controller integration and hardware–software interaction within SoC or networking-oriented designs.
- Ability to work across multiple projects simultaneously and adapt to a fast-paced, highly technical development environment.
- Demonstrated technical leadership, including ownership of complex design blocks, driving architecture discussions, and mentoring engineers.
- Experience with industry-standard control and configuration interfaces (e.g., I2C, SPI, SMBus) is a plus.
- Experience with SystemVerilog-based verification techniques (e.g., assertions, self-checking testbenches, constrained stimulus) is a plus.
- Exposure to low-power design techniques, power-aware RTL design, or clocking strategies is a plus.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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