Title: Senior Engineer Volatile Memory Bitcell Simulation and Modeling
About GlobalFoundries:
GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.
Introduction:
As an engineer for volatile memory simulation and modeling, you will support our technology teams across our 22 nm fully depleted SOI and 12 nm finfet technologies. Your work will be focused on creating or updating SPICE models for volatile memory bit cells as well as SPICE simulation of these bit cells.
You will be a member of the Global Memory Solutions team with colleagues located in Bangalore, Germany and the United States.
Your Job:
- Definition of suitable test structures to be used for modeling measurements.
- Test program definition and submission for modeling tests.
- Evaluation of the results and definition of model targets.
- Evaluation whether the models meet the intended bit cell targets by SPICE simulations.
- High sigma SPICE simulations of expected yield and comparison with measured array data.
- Debugging technology issues with the help of SPICE simulations.
- Prediction of expected yield, read current and leakage for future bit cells.
- Parasitic extraction of bit cell kits and test structures.
- Maintenance and improvement of model and simulation infrastructure.
Other Responsibilities:
- Once you are competent in the items mentioned above, your responsibility may extend to the following responsibilities:
- Bit cell test structure layout and verification.
- Bit cell enablement in the PDK in close cooperation with the PDK team.
- Bit cell kit layout and verification in close cooperation with the technology owners, the Integration teams and OPC.
- Maintenance and improvement of the layout infrastructure for memory bit cells.
- Analysis of incoming designs for memory content.
- Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.
- This job requires close cooperation with global internal teams. In addition, some interaction with customers and IP providers will be part of your job.
Required Qualifications:
- Master's degree in microelectronics, electrical engineering, physics, or related fields from 2025
- Experience with SPICE models and simulations of MOSFETs and SRAM or other volatile memory cells.
- In-depth understanding of MOSFET SPICE models.
- Basic knowledge in scripting with R.
- Experience with high sigma simulations of SRAM bit cells.
- Detailed knowledge about semiconductor process flow and technology, preferably for highly scaled technologies down to 22 nm and 12 nm
- Good understanding of semiconductor device physics, especially MOSFETs.
- Good understanding and experience with SRAM bit cell functionality and characterization.
- Knowledge about other types of volatile memory bit cells.
- Travelling may be required for certain projects but is expected to be less than 10%. For the initial training, there may be an extended stay of up to 3 months in the US required.
- Fluency in English Language – written & verbal
- Very good analytical and presentation skills.
Preferred Qualifications:
- For the second stage of your career the following qualifications will be required:
- Experience in layout and design with Cadence Virtuoso including use of DRC and LVS verification versus schematics as well as Skill coding.
- Familiar with scripting languages like Pearl, shell script, Python
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