At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Role Overview
We are seeking a senior individual contributor to design, build, and optimize core debug and verification components used across our EDA product stack. You will own high-impact systems that bridge hardware and software, deliver reliable correlation across RTL and gate-level views, and accelerate waveform reconstruction at scale. This role emphasizes strong C++ engineering, deep verification knowledge, and hands-on problem solving in production environments.
Key Responsibilities
- Own and advance HW/SW debugging flows, including integration with ELF/DWARF formats, GDB RSP, and IDE/tooling (e.g., Eclipse plugins) to streamline co-debugging for complex designs.
- Implement and maintain RTL-to-gate correlation features (CRDB/NPI, SVF-based mapping), ensuring accurate, on-demand loading and consistent cross-view analysis.
- Lead performance optimization for waveform reconstruction engines, leveraging modern concurrency frameworks (e.g., Intel TBB) and native APIs to reduce runtime and memory footprint.
- Develop expression evaluators for SystemVerilog and related languages to enable fast, reliable signal and assertion analysis.
- Integrate coverage (e.g., gcov/lcov) across HW/SW flows and ensure data model compatibility (DWARF5 and newer).
- Collaborate cross-functionally with global teams (US/India/Germany/Japan) to align architecture, deliverables, and quality standards; provide technical leadership and code reviews.
- Contribute to waveform tooling for SystemC and related modeling environments to enhance visibility and debug productivity.
Minimum Qualifications
- 17+ years of professional experience in EDA software development, with expert-level C++ and strong SystemVerilog skills.
- Proven expertise in HW/SW co-debugging, RTL-gate correlation, essential signal analysis, and large-scale debug infrastructure.
- Hands-on knowledge of ARM and RISC-V architectures; familiarity with ELF/DWARF, GDB RSP, and related standards.
- Proficiency with regular expressions, Perl, Shell, Tcl, and Python for tooling and automation.
- BS/MS in Electrical Engineering or Computer Science (or equivalent experience).
Preferred Qualifications
- Demonstrated impact in performance engineering (e.g., Intel TBB study/implementation) for high-throughput waveform reconstruction.
- Experience building SystemVerilog expression evaluators and extending debug/coverage toolchains.
- Background in data model design (e.g., new DB formats enabling on-demand loading) for scalable analysis pipelines.
- Contributions to SystemC waveform dumper and native API integrations to accelerate I/O.
- Track record of technical leadership (e.g., mentoring 7+ engineers while remaining hands-on with coding and architecture).
- Experience with Eclipse plugin development and cross-platform tool integration.
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