The Role and Impact
As a Silicon Packaging Design Engineer, you will play a critical role in the development of advanced substrate designs that drive Intel's innovation and technological leadership. This position offers a unique opportunity to contribute to cutting-edge technologies by managing the end-to-end development process of substrate designs, from concept to tapeout. You will collaborate with silicon and hardware teams to optimize design performance, cost efficiency, and manufacturability, ensuring Intel remains at the forefront of high-performance applications. Your contributions will directly impact Intel's ability to deliver world-class solutions that address global challenges in computing.
Key Responsibilities
Drive the physical layout and routing of package designs, ensuring alignment with silicon, package, and board performance requirements.
Conduct substrate fit and routing studies to establish design, performance, and cost tradeoffs.
Define and implement substrate design rules, conducting internal and external reviews to maintain quality standards.
Analyze data, resolve Design Rule Checks (DRCs), and optimize designs for manufacturability and performance.
Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions.
Complete documentation and collateral into the product lifecycle management system of record.
Strong analytical ability and problem-solving skills, including debugging and providing innovative solutions.
Minimum Qualifications
This position is not eligible for Intel sponsorship.
US Citizenship
Bachelor's degree in Electrical Engineering, Mechanical Engineering, or Material Sciences, with 0-1+ years of relevant experience, or related field.
Experience with package design tools such as Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.
Experience with physical layout aspects of substrate design, including custom layouts, floor plans, or schematic layout conversions.
Experience microelectronic package or PCB physical layout design and manufacturing processes.
Preferred Qualifications
Master Degree in Electrical Engineering, Mechanical Engineering, or Material Sciences or related field.
Experience in substrate design or I/O routing, or technology development.
Experience with microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS.
Experience with scripting using Python, VB, C, or similar languages.
Join Intel and contribute to shaping the future of technology. Be a part of a dynamic team committed to delivering innovative solutions that address the needs of a rapidly evolving world. Apply today to take the next step in your career.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $91,150.00-172,860.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.