Job Details:
Job Description:
The engineer is responsible for the physical design of high-density package substrates for Intel SoCs. The engineer must have a good understanding of flip chip interconnect based leading edge substrate design rules along with package assembly driven constraints and rules. The role requires the engineer to collaborate and work with multiple stakeholders spread across different geos, in a fast-paced environment, from pathfinding phase to the package substrate tape out. Must have experience of at least delivering 2 high density flip chip interconnect-based package designs, with engagement from planning/pathfinding phase to Tape Out. The design engineer must have a strong understanding of the complete Package design flow related to flip chip designs. The responsibilities include:
- Working with Full chip/IP development teams to drive and plan optimal bump patterns, meeting the electrical/performance requirements, substrate and assembly design rules, and cost targets.
- This requires to lead the design efforts and develop multiple design options swiftly in a dynamic cross-functional environment during the design cycle.
- Driving the substrate physical design reviews as per plan, and meet the schedule and quality expectations. - Validating the design using design validation tools.
- Ensuring timely release/tape out of cost optimal high quality package substrates, after reviews with internal stakeholders and with the package substrate manufacturing vendors.
- Identifying areas for improvement - for ex: design tool features, design efficiency, design methods, and proactively seeking to partner with experts/teammates to drive the improvements.
Qualifications:
Experience/Competencies:
- 5 -7 years of experience in the development of competitive Packages for high-speed products like CPUs/ASICs/Chipsets/GPUs.
- Must have led at least 2 PKG designs from Path Finding Phase to PKG Tape Out.
- Strong understanding of package substrate design and package assembly rules.
- Must have solid experience in designing packages with Mentor Graphics (Expedition).
- Exposure to different Package technologies, an advantage.
- Proven stakeholder management skills, in a global set-up, with technical teams spread across different geos.
- Master's in Electrical/Mechanical/Materials Sc and Engg with 2+ years experience or Bachelor's with 5+ years experience.
- Cross-functional experience and proven self-learning abilities with new design tools, flows, and methods will be advantageous.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
As a member of the Chief Technology Office, Artificial Intelligence, and Network and Edge Group (CTO AI NEX), you will be committed to strategically penetrating the AI market by delivering disruptive and transformative solutions. Your focus will be on leveraging technology innovation and incubation to drive commercial success, ensuring that advancements create significant value. The team is dedicated to driving the software-defined transformation of the world's networks profitably, setting new standards for efficiency and connectivity. Through these priorities, you aim to lead the way in technological evolution and redefine the future of global networks.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.