Intel Foundry Technology Development is seeking a Silicon Design Rule Owner (DRO) to join the Advanced Design and Customer Enabling team, supporting a broad range of product families.
The Design Rule Owner serves as the technical authority responsible for defining, validating, governing, and maintaining assembly-related design rules that ensure robust chip packaging, assembly yield, reliability, and manufacturability. This role bridges silicon design, package design, assembly process technology, OSAT and factory partners, and reliability engineering.
The DRO collaborates closely with product design and architecture, fabrication, assembly platform pathfinding and development, and customer enabling teams to define and drive design rules that enable competitive products while meeting cost and manufacturability requirements.
A key aspect of this role is engagement from the earliest stages of silicon and package technology and product concept through product design tape-out. The DRO works across multiple product families, packaging technologies, and silicon nodes to deliver a consistent design rule strategy and a forward-looking, industry-leading design rule roadmap.
This position involves extensive cross-disciplinary and cross-organizational collaboration, direct interaction with product designers, and engagement with external suppliers and customers.
The DRO also partners with EDA teams to implement design rule checks and verification flows, reduce false violations, and support rule waivers and exceptions. The role includes maintaining authoritative design rule documentation, change logs, and revision history, and enforcing consistency across product designs.
Key Skills:
Silicon and package assembly design rule definition and governance
Semiconductor assembly and packaging process knowledge
Design rule validation, verification flows, and EDA tool integration
Data analysis and technical problem solving
Collaboration across silicon design, packaging, fab, assembly, and reliability teams
Management of design rule waivers, exceptions, and false violations
Authoring and maintaining technical documentation (DRMs, change logs, revisions)
Clear technical communication and stakeholder alignment
Strong organizational and time management skills
Ability to operate effectively in ambiguous, early-technology environments
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelor's degree in electrical/mechanical/chemical/materials Science engineering or related field with 6+ years of experience
-OR- a Master's degree in electrical/mechanical/chemical/materials Science engineering or related field with 4+ years of experience
- OR- a PhD in electrical/mechanical/chemical/materials Science engineering or related field with 2+ years.
Related years of experience should include:
-Design rule verification in EDA tools
Preferred Qualifications:
Silicon and package assembly design or design rule development
Semiconductor assembly and packaging process knowledge
Design rule validation, verification flows, and EDA tool integration
Collaboration across silicon design, packaging, fab, assembly, and reliability teams
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.