About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Marvell Physical Design team is located in our Burlington, VT office, and has a long history of successful design tapeouts in advanced process nodes. Our team is made up of both newer and more experienced engineers with a broad depth of static timing analysis and physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you’ll have the opportunity to work on both the timing analysis and methodology for future designs of our next-generation, high-performance processor, and data center chips in a leading-edge CMOS process technology.What You Can Expect
Work with teams across various disciplines such as PD/Digital/RTL/Analog to ensure design convergence and integration in a timely manner
Perform Static Timing Analysis and design timing convergence and closure on multi-voltage designs using industry standard EDA tools (PrimeTime preferred)
Work with RTL design teams to drive assembly and design closure
Collaborate with physical design engineers to drive designs to timing closure
Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes
Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation
What We're Looking For
Basic Qualifications:
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree
Expertise in full-chip & sub-hierarchy integration
Experience integrating and taping out large designs utilizing a digital design environment
Good understanding of RTL to GDS flows and methodology
Good scripting skills in TCL/Python
Knowledge of Verilog
Preferred Qualifications:
Static Timing Analysis expertise and experience
Expertise in Static Timing Analysis using industry-standard STA tools (PrimeTime preferred)
Experience driving timing closure and taping out large designs utilizing a digital design environment
Experience with advanced Clock Tree Synthesis and Analysis techniques
Experience closing timing in a Tessent DFT based design
Experience with Cadence Innovus
Experience with PrimeTime
Familiarity with machine‑learning–assisted or data‑driven timing methodologies
Experience with ECO implementation and analysis (functional and timing ECOs)
Knowledge of UPF and low‑power design methodologies
Expected Base Pay Range (USD)
0 - 0, $ per annumThe successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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