Senior/ Staff Physical Design Engineer - EMIR & Power Integrity

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR & Power Integrity to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will execute the Electro-Migration and IR Drop (EMIR) analysis and sign-off from block level to full-chip, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. You will be responsible for validating power grid architectures to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the world’s most demanding AI and cloud environments.

Key Responsibilities

• Execute static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from the block level through to full-chip sign-off
• Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
• Work with Physical Design teams to implement optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
• Collaborate closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
• Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
• Perform root-cause analysis for voltage drop violations and EM risks, proposing and implementing layout fixes alongside the PD team
• Verify current density rules for ESD protection networks and ensure compliance with strict foundry reliability constraints
• Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

Basic Qualifications

• Bachelor's or Master's degree in Electrical Engineering or a related technical field
• 5+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products
• Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, Totem, or Cadence Voltus)
• Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm), including fin-heating, thermal coupling, and layout-dependent effects
• Solid understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture
• Proven ability to debug complex voltage drop issues, identify "weak spots" in the grid, and drive convergence on large, complex designs
• Proficiency in Python, Tcl, or Perl for flow automation and data parsing

Preferred Experience

• Experience with AI, networking, PCIe, CXL, or large-scale SerDes integration
• Background in Analog/Mixed-Signal EMIR analysis (using Totem or specialized analog flows)
• Experience performing Chip-Package-System (CPS) thermal and power co-simulation
• Familiarity with thermal analysis tools and their interaction with electrical performance
• Experience working with sign-off criteria and margins for high-volume production chips