Senior Clock Architecture & Design Engineer

Job Details:

Job Description:

Join a team that defines the heartbeat of next-generation CPUs.

We are looking for a Senior Clock Architecture & Design Engineer  a pivotal role in developing the clocking architecture for Intel's next-generation flagship CPUs. You'll work at the cutting edge of semiconductor technology, implementing clock solutions on the industry's most advanced process nodes.

What You'll Do

Drive Innovation in Clock Architecture:

• Architect and implement sophisticated clock distribution networks for high-frequency flagship CPU designs
• Pioneer custom clock solutions that push the boundaries of performance and power efficiency
• Design breakthrough custom circuits and library cells that enable next-generation processor capabilities

Lead Technical Excellence:

• Develop and optimize advanced clock tree synthesis flows for complex, multi-billion transistor designs
• Collaborate with world-class architecture, physical design, and validation teams to deliver industry-leading solutions
• Interface with cutting-edge EDA vendors to shape the future of design automation tools

Make Your Mark

• Contribute to products that power millions of devices worldwide
• Work on flagship CPU designs that define industry standards
• Solve complex technical challenges in a fast-paced, innovation-driven environment

Behavioral traits that we are looking for:

• Exhibits strong problem ownership and follows designs through architecture, implementation, and signoff
• Uses data‑driven decision‑making to resolve complex technical tradeoffs
• Influences design direction through collaboration and technical expertise
• Adapts effectively to changing priorities in a fast‑paced development environment
• Provides technical guidance or mentorship as appropriate within project teams
• Demonstrates consistency, reliability, and accountability in meeting project commitments

Why This Role Matters

This isn't just another engineering position, it's an opportunity to influence the performance of Intel's most critical products. You'll work with cutting-edge technology, collaborate with industry experts, and see your innovations impact computing performance worldwide.

Ready to engineer the future of high-performance computing?

This role offers the perfect blend of technical depth, innovation opportunity, and career growth within one of the semiconductor industry's most respected teams.

Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. 

See  Intel Benefits for more details. 

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
 

Minimum qualifications and experience that will get you noticed:

Bachelor's in Electrical/Computer Engineering or related STEM field  and 5+ years of experience.  Or a Master's  in the same field and 3+ years  of experience or a PhD  and 1+ years experience.

Your experience listed above must be in the following:

• Experience in physical design, clock tree synthesis (CTS) and static timing analysis
• Strong background in custom circuits, transistor-level design and spice simulations
• Strong programming skills and proficiency in industry-standard scripting languages 

Preferred qualifications and experience that will make you stand out:

• Hands on experience in high frequency custom clock network design on leading edge technology nodes
• Experience in clocking architecture, PLL/DLL architecture and design
• Expertise in timing constraint adaptation and timing closure methodologies 
• Expertise in fullchip design tools and flows

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Texas, Austin

Additional Locations:

US, Oregon, Hillsboro

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.