Hitachi

R&D Senior Engineer (package integration)

Genoa, Ligura, Italy Full time

Location:

Genoa, Ligura, Italy

Job ID:

R0125667

Date Posted:

2026-05-05

Company Name:

HITACHI ENERGY ITALY S.P.A.

Profession (Job Category):

Engineering & Science

Job Schedule: 

Full time

Remote:

No

Job Description:

The opportunity
Hitachi, Ltd. is seeking an experienced R&D Senior Engineer to lead and contribute to the development and integration of advanced packaging solutions for cutting-edge technologies. This role involves driving innovation in package design, material selection, and process optimization to ensure high performance, reliability, and manufacturability of our products.

How you'll make an impact
* Lead the design, development, and characterization of advanced semiconductor packages, including 2.5D/3D integration, Wafer Level Packaging (WLP), and System-in-Package (SiP) solutions.
* Conduct feasibility studies and evaluate new packaging technologies, materials, and processes to meet future product requirements.
* Collaborate closely with cross-functional teams including chip design, process engineering, manufacturing, and reliability to define package specifications and ensure seamless integration.
* Perform detailed package simulations (mechanical, thermal, electrical) to optimize performance and predict reliability.
* Develop and execute comprehensive test plans for package characterization and reliability validation.
* Identify and resolve complex technical challenges related to package integration, material interactions, and manufacturing processes.
* Generate technical reports, presentations, and patent disclosures to document research and development efforts.
* Mentor junior engineers and contribute to a culture of innovation and continuous improvement within the R&D team.
* Stay abreast of industry trends, emerging technologies, and competitive landscape in semiconductor packaging.

Your background
* Master's or Ph.D. in Electrical Engineering, Mechanical Engineering, Materials Science, or a related field.
* Minimum of 7 years of experience in semiconductor packaging R&D, with a strong focus on advanced packaging integration.
* Demonstrated expertise in at least two of the following areas: 2.5D/3D integration, Wafer Level Packaging (WLP), System-in-Package (SiP), or advanced flip-chip technologies.
* Proficiency with package design software (e.g., Cadence, Ansys, COMSOL) and simulation tools.
* Strong understanding of package materials (e.g., substrates, interconnects, encapsulants) and their properties.
* Experience with package reliability testing methodologies and failure analysis techniques.
* Familiarity with semiconductor manufacturing processes and equipment.
* Excellent problem-solving, analytical, and critical thinking skills.
* Strong communication, interpersonal, and presentation skills, with the ability to collaborate effectively in a global team environment.
* Ability to work independently and manage multiple projects simultaneously.

More about us

We offer you the opportunity to work with fantastic people and develop yourself on projects that present great technical challenges and have a real impact. 

Wide range of benefits: 

  • Health insurance; 

  • Pension fund; 

  • Welfare; 

  • Smart working; 

  • Flexible working hours; 

  • Lunch ticket.

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