Principal Physical Design Engineer
Company: NXP India Pvt. Ltd. (Pune)
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Job Summary
NXP India Pvt. Ltd. is seeking a highly experienced and technically adept Principal Physical Design Engineer to lead and contribute to the physical implementation of complex SoC and IP designs. This role involves driving all aspects of the physical design flow from netlist to GDSII, ensuring performance, power, and area (PPA) targets are met for cutting-edge semiconductor products.
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Job Responsibilities
As a Principal Physical Design Engineer, you will be responsible for:
* Leading the physical implementation of challenging digital blocks and sub-systems, from synthesis to GDSII, for advanced technology nodes.
* Driving and optimizing the entire physical design flow, including floorplanning, power planning, place & route, clock tree synthesis (CTS), timing closure (STA), signal integrity analysis, and physical verification (DRC/LVS/ERC).
* Developing and implementing innovative solutions to address complex PPA (Power, Performance, Area) challenges and achieve aggressive design targets.
* Collaborating closely with design, architecture, and DFT teams to understand design requirements and resolve implementation issues.
* Mentoring junior engineers, providing technical guidance, and contributing to the development of best practices and methodologies.
* Evaluating and integrating new EDA tools and flows to enhance efficiency and design quality.
* Participating in design reviews, providing expert input, and ensuring adherence to quality and release criteria.
* Proactively identifying and mitigating potential risks in the physical design flow.
* Documenting design methodologies, scripts, and results for knowledge sharing and future reference.
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Job Qualifications
To be successful in this role, you should possess the following qualifications:
* Education: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
* Experience: 10+ years of hands-on experience in physical design of complex SoCs or IP blocks, preferably at advanced technology nodes (e.g., 16ffc, 7nm, 5nm).
* **Technical Skills:**
* Expertise in industry-standard physical design EDA tools (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus, Ansys RedHawk, Mentor Calibre).
* Strong understanding of all aspects of physical design: floorplanning, power grid design, placement, clock tree synthesis, routing, and sign-off checks.
* Deep knowledge of static timing analysis (STA) principles, timing closure techniques, and constraint development.
* Proficiency in power analysis and optimisation techniques (leakage, dynamic power).
* Experience with signal integrity analysis, IR drop analysis, and electromagnetic.
* Solid understanding of physical verification (DRC, LVS, ERC) and DFM considerations.
* Familiarity with scripting languages (Tcl, Perl, Python) for automation and flow development.
* Experience with low-power design techniques (UPF/CPF, multi-voltage design).
* Strong analytical and problem-solving skills, with a keen eye for detail.
* Soft Skills:
* Excellent communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams.
* Proven ability to lead technical initiatives and mentor junior engineers.
* Strong self-motivation and ability to work independently as well as in a team environment.
* A proactive attitude towards problem-solving and continuous improvement.