Key Responsibilities:
Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation (PLLs, DLLs), distribution, gating, and domain crossing strategies.
Define and optimize power-performance-area (PPA) trade-offs for complex clocking and circuit topologies.
Collaborate cross-functionally with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP.
Own the technical roadmap and methodology improvements for clocking, timing closure, and custom circuits.
Mentor and technically guide a team of junior and senior designers.
Review and approve specifications, schematics, simulations, and post-layout signoff for high-reliability silicon meeting clock and circuit specs.
Partner with foundries, EDA vendors, and internal silicon validation teams to ensure robust silicon correlation and yield.
Required Qualifications:
M.Tech / B.Tech / Ph.D. in Electrical/Electronics Engineering or related field.
15–20 years of hands-on experience in SoC clocking, custom analog/digital circuit design, and timing architecture.
Proven expertise in clock tree synthesis (CTS), clock gating, low-power techniques, and glitch-free clock domain crossing.
Deep experience with PLL/DLL architecture, design, and integration in SoCs.
Strong background in transistor-level design, spice simulations, and post-layout validation.
Familiarity with EDA tools and scripting (TCL, Perl, Python).
Experience leading multi-disciplinary teams and working across global sites.
Excellent communication, documentation, and project leadership skills.
Preferred Qualifications:
Background in high-speed interface IPs, power management circuits, or custom memory design.
Experience with Server, AI/ML, or networking SoCs.
Exposure to Silicon bring-up, characterization, and debug.
Previous patents or publications in the area of clocking or circuit design.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.