Job Details:
Job Description:
About the Group:
Central Engineering Group (CEG) oversees all test chip design, all foundational and hard IP, all EDA and design platform functions for Intel Products, as well as all external IP and EDA commercial licensing. The Central Engineering group is also responsible for delivering industry-leading Custom Silicon Solutions for Intel Customers in the Client and Hyperscaler Domains.
About the Role:
Intel’s Central Engineering Group is seeking a Silicon Packaging Architect, responsible for bridging silicon design and advanced packaging to deliver high-performance, cost-effective solutions for next-generation SOCs and DDR PHY interfaces.
Key Responsibilities:
- Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs.
- Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts.
- Conduct hands-on package extractions and simulations (signal integrity, power integrity) to assess package trace and electrical impacts, and perform risk assessments for bump-out strategies.
- Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases.
- Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed).
- Focus on design, development, and architecture, not process or materials engineering.
Required Experience:
- Experience in both silicon design (preferably mixed signal/analog) and packaging co-design.
- Background in DDR, SOC, or similar high-speed interface development.
- Hands-on expertise with bump mapping, floor planning, and packaging constraints.
- Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation.
- Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required.
- Individual contributor or principal engineer level preferred; management experience is not required.
- Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia).
Qualifications:
- Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master’s or Ph.D. preferred).
- 10+ years in silicon and packaging co-design
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Business group:
The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US:
$214,730.00-303,140.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.