Principal Digital Design Engineer – Wireline PHYs

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

As a Digital IC Design Principal Engineer with Marvell, you’ll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Data Center Connectivity, Custom Silicon, and Switches.

We are seeking an experienced and driven Principal Digital Design Engineer to join our team developing high-performance wireline PHY IPs for advanced SoCs and ASICs. This role focuses on the digital design and integration of physical layer (PHY) components, including multi-gigabit SerDes and digital control/adaptation logic interfacing with analog/mixed-signal circuitry.

You will play a key role in delivering next-generation PHY solutions for SerDes, Die-to-Die interconnects, and Parallel Optics, optimized for advanced nodes, low power, and high performance. This is a cross-disciplinary engineering role offering the opportunity to innovate at the boundary of digital, analog, and system design.

What You Can Expect

• Digital Design for PHYs: Architect, design, and implement RTL for key digital blocks used in PHYs, including adaptation engines, calibration logic, control/state machines, test features, and DSP pipelines.
• Mixed-Signal Interface: Collaborate with analog/mixed-signal teams to define control interfaces, adaptation loops, and digital support for real-time calibration and equalization (e.g., DFE, CTLE, CDR support).
• Application Focus: Design PHY digital systems targeted for SerDes, Die-to-Die interfaces, and Parallel Optics, ensuring robust operation across voltage, temperature, and process corners.
• RTL Implementation & Verification: Develop synthesizable, lint-clean, CDC/RDC-aware RTL using Verilog/SystemVerilog. Collaborate with verification teams to ensure functional and coverage closure.
• Timing & Integration: Drive floorplan-aware and timing-closure-friendly design practices. Work closely with the physical design team to ensure optimal layout and integration of PHY IP into larger SoCs.
• Microcontroller Integration: Define and implement bus interfaces (e.g., APB, AHB, AXI) and register maps to enable seamless communication between PHY digital logic and embedded microcontrollers.
• Bring-up & Debug Support: Assist validation and post-silicon teams with lab bring-up, debug, and characterization of PHY behavior in hardware environments.
• Mentorship & Leadership: Provide technical leadership to junior engineers, participate in design reviews, and contribute to internal methodology and process improvements.
   

What We're Looking For

• Master’s degree in Electrical Engineering, Computer Engineering, or related field with 7+ years of relevant experience, or PhD with 4+ years of relevant experience.
• Extensive experience in digital design, with a strong focus on high-speed PHY or SerDes development.
• Expertise in RTL design using Verilog/SystemVerilog, with deep knowledge of synthesis, timing closure, and CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) design techniques.
• Solid understanding of logic synthesis and static timing analysis (STA), including constraints development and timing closure at block and chip levels.
• Strong understanding of system-level design and integration with embedded microcontrollers, including bus protocols (e.g., APB, AHB, AXI), register map definition, firmware interfacing, and interrupt/event control.
• Experience developing control logic, DSP blocks, and adaptation/calibration systems for PHYs.
• Solid understanding of analog/digital co-design challenges in mixed-signal PHY development.
• Proficient with EDA tools for simulation, synthesis, lint, CDC/RDC analysis, and timing analysis.
• Familiar with scripting languages (e.g., Python, Perl, TCL) for design automation and flow customization.
• Strong problem-solving and debug skills, including post-silicon bring-up and lab correlation.
• Knowledge of DFT, BIST, and scan insertion for mixed-signal designs.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity
 

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
 
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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