Memory Layout Lead

Job Details:

Job Description:

You will be a key member of the Corporate Memory Organization (CMO) Layout Team, driving advanced layout design development for Memory Compilers.

In this senior role, you will work with broadly defined parameters on complex and non-standard assignments while providing technical leadership and mentorship. Your responsibilities will include but not be limited to:

Core Technical Responsibilities:

• Drive physical layout implementation of memory building blocks including control circuits, sense amplifiers, I/O blocks, bit cell arrays, and decoders within a compiler framework, demonstrating deep understanding of memory compiler floorplans and top-level integration strategies.
• Bridge cross-functional collaboration between circuit engineering, design automation, and mask design teams, serving as the technical interface and subject matter expert.
• Execute comprehensive layout development encompassing transistor/device cell level planning, layout implementation, assembly, and advanced routing techniques for next-generation memory technologies.
• Demonstrate mastery of all layout aspects including advanced Computer-Aided Design (CAD) tool utilization, productivity macro development, and deep expertise in layout methodologies and workflow optimization

Technical Leadership and Decision Making:

• Provide expert engineering judgment for critical decision-making and complex design trade-offs, including advanced IR drop analysis and mitigation, Reliability Verification (RV) analysis, ECO impact assessment, and project schedule optimization.
• Drive methodology innovation and process refinement for memory compilers in close collaboration with Design Automation (DA) teams and senior/principal design engineers.
• Lead technical assessments of complex layout assignments, establish realistic project timelines, manage multiple concurrent deliverables, and ensure on-time delivery while maintaining quality standards.

Leadership and Collaboration:

• Mentor and guide junior layout engineers, providing technical guidance and knowledge transfer.
• Lead cross-functional initiatives and serve as the primary technical contact for memory layout projects.
• Drive continuous improvement in layout efficiency, quality metrics, and design methodologies.
• Collaborate with global teams and effectively communicate complex technical concepts to diverse stakeholders.
• Contribute to strategic planning for future memory compiler architectures and layout automation roadmaps.

This position offers the opportunity to work on cutting-edge memory technologies while leading technical initiatives and developing the next generation of layout engineering talent.

#DesignEnablement

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in Electronic/Microelectronic Engineering, Computer Engineering, or a related engineering discipline.
• 10+ years of custom digital/analog layout design experience; memory layout experience is preferred.
• Proficiency in industry-standard layout tools (e.g., Cadence Virtuoso, Synopsys Custom Compiler).
• Basic programming skills (UNIX shell scripting, Tcl, Perl).
• Strong understanding of semiconductor fabrication processes and design rules.
• Experience with DRC/LVS/RV verification and debugging.

Preferred Qualifications:

• Layout design experience with memory compilers and memory architectures.
• Layout automation and scripting experience.
• Advanced programming skills in Python or other scripting languages
• Experience with advanced technology nodes (14nm and below)
• Knowledge of FinFET or advanced device technologies
• Experience mentoring junior engineers and leading design projects

#DesignEnablement

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location:

Malaysia, Penang

Additional Locations:

Business group:

Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.