Memory Electrical Validation Engineer

Job Details:

Job Description:

The primary responsibilities for this role will include, but are not limited to:

• Defines electrical validation strategy for memory IO interfaces to achieve optimized electrical performance and meet product production goals.

• Validates circuit analog performance, electrical signal integrity compliance to industry standard specifications, and system level margin for stable operation and production target prediction.

• Defines MRC (Memory Reference Code) requirements for validation and margin optimization and analyzes, validates, debugs, and optimizes MRC steps and values to optimize margins and quality.

• Conducts and participates in multidisciplinary research in the design, development, testing, validation, and utilization of memory IO and mixed signal architectures inclusive of industry standard datacom applications and custom Intel interfaces.

• Develops procedures, analysis, and designs for validation, validation infrastructure, and systems margin validation.

• Analyzes internal and external customer returns with emphasis on improving yields and driving test escape closure.

• Applies and uses independent evaluation to select components and equipment based on analysis of specifications, performance, and reliability.

• Performs debug to identify root causes and resolve all functional and triage failures for electrical issues.

• Tests interactions between various electrical design features using validation infrastructure.

• Applies understanding of DFT and DFM to collaborate with architecture, design, and presilicon verification teams to ensure capability to validate and test IO architecture implementations.

• Prepares validation specifications, evaluates IP, and generates test reports.

• Ensure products conform to standards and specifications.

Qualifications:

Minimum Qualifications:

Minimum qualifications are required to be initially considered for this position.

• Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field.

• 4+ years of relevant working experience.

• Hands-on experience with memory architecture and protocols such as DDR5 and LPDDR5.

• Intermediate knowledge of MRC (Memory Reference Code), JEDEC specifications, DRAM architecture, and Signal Integrity validation.

• Experience with Memory Controller design and DDR physical layer (DDR PHY) or DDRIO.

• Intermediate to Advanced English proficiency.

• Must have unrestricted, permanent right to work in Mexico.

This position is not eligible for employment-based visa/immigration sponsorship.

This position is for Guadalajara location only. Relocation is not approved.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Mexico)

Primary Location:

Mexico, Guadalajara

Additional Locations:

Business group:

At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.