Job Details:
Job Description:
The Role and Impact
Join Intel's dynamic team as an IP Logic Design Engineer, where you will play a pivotal role in shaping the future of cutting-edge semiconductor technologies. You will be part of an innovative team responsible for designing and optimizing Intellectual Property (IP) blocks critical to next-generation Server and Client System-on-Chip (SoC) designs. Your contributions will directly drive advancements in low-power, high-performance architectures, ensuring Intel remains at the forefront of the industry. This position offers the opportunity to collaborate with world-class engineers, tackle complex technical challenges, and make a significant impact on Intel's success.
Key Responsibilities
- Develop and implement Register Transfer Level (RTL) coding and simulation for IP blocks required for integration into SoC designs.
- Collaborate on defining architecture and microarchitecture features of the IP blocks, ensuring alignment with system requirements.
- Optimize logic designs to meet power, performance, area, and timing goals, ensuring design integrity for physical implementation.
- Perform RTL debug and resolve test failures to ensure feature correctness and high-quality IP delivery.
- Drive quality assurance measures for seamless IP-SoC handoff and integration.
- Execute front-end quality checks, including CDC, RDC, LINT, Synthesis, and timing closure.
- Review verification plans, ensuring accurate validation of design features and addressing implementation corrections as needed.
- Support SoC customers for successful IP integration and verification within their systems.
Qualifications:
Minimum Qualifications
- Proficiency in RTL design, System Verilog, Verilog, and low-power design methodologies.
- Strong understanding of SoC architecture, IP requirements, and microarchitecture fundamentals.
- MMU will be added plus
- Experience with tools such as CDC, RDC, LINT, synthesis, and timing closure.
- Advanced knowledge of protocols including PCIe, AXI, AHB, and APB.
- Technical expertise in debugging RTL designs and writing verification testbenches.
- Hands-on experience with UPF low-power coding and debug.
- Knowledge of clock gating, clock domain crossing, and power gating techniques.
- Familiarity with scripting languages such as TCL and technical documentation practices.
Preferred Qualifications
- Master's degree Electronics Engineering, Computer Engineering, or related field with 8+years.
- 10+ years of experience with B.tech in Electronics Engineering, Computer Engineering, or related field in digital design, RTL coding, and design optimization.
- MMU will be added plus
- Proven ability to collaborate across functional teams and solve complex design challenges.
- Strong communication skills and ability to articulate technical concepts effectively.
Explore the opportunity to contribute to Intel's cutting-edge innovation and be part of a team building transformative technologies. Apply today to elevate your career and drive impactful change in the semiconductor industry.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.