Intel

Formal Verification Engineer - CPU Core

US, California, Folsom Full time

Job Details:

Job Description:

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone.

Life at Intel

We're looking for a motivated and talented engineer to join the US CPU verification team. In this role you will be critical to the development of next generation CPU's designed to power the AI revolution.



You will join the team responsible for exhaustively verifying the architecture and micro-architecture changes implemented in the CPU using a combination of dynamic and formal verification methods.

Job responsibilities include writing verification test plans, and then writing tests to execute those plans. Development of pre-silicon verification collateral (such as behavioral checkers, coverage monitors, test generators or score-boards) is often required to enable test plan execution.

On Formal front, responsibilities may include technical ownership of formal verification of a microarchitecture block, methodology, or otherwise significant aspect of the Big Core CPU, Understand and contribute to micro-architecture specification and define the formal verification strategy for a significant portion of the design, Lead ROI analysis and recommend appropriate use of formal verification vs dynamic validation techniques for relevant parts of the CPU.

Candidates will need to debug failing tests, then work with designers and architects to resolve bugs. Successful verification engineers can anticipate failure modes, and write punishing test content to stress the design and identify bugs. Candidate will analyze coverage gaps and devise strategies to fill coverage holes. The quality of the design and the final product is directly proportional to the quality of the design verification work. The job involves working with Global RTL, Arch DV and Formal teams to define verification strategy, planning and execution, driving verification methodologies etc.

Behavioral traits for this position include:
- Strong problem solving
- Tolerance of ambiguity
 

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.

Minimum Qualifications:

Candidate must have a Bachelors degree in Computer Engineering or Electrical Engineering or related STEM field and 2+ years of relevant work experience - OR - a Masters degree in Computer Engineering or Electrical Engineering or related STEM field and 1 year of relevant work experience.

1+ years’ experience in/with:
o In-depth computer architecture knowledge with emphasis on out of order processor execution, memory hierarchy, and memory management
o Hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools
o Assertion writing, checker development, coverage analysis, failure debug, root cause analysis
o Programming in at least one language: C/C++, Java, Specman E etc. and familiarity with any of scripting languages: Perl, Python, Ruby, TCL
o Intel or industry experience in pre-silicon verification of CPU cores, including specific areas of technical ownership/expertise relevant to CPUs
o Industry standard formal verification tools such as JasperGold, IFV, Questa Formal, VC Formal


Preferred Qualifications:
o Knowledge of Intel Architecture ISA and system architecture, x86 assembly language.
o Pre/Post-silicon debug and analysis
o Research publications, patent filings, or other evidence of personal technical innovation in validation methodology advancement.

o Applying sequential equivalence checking in complex micro-architectures
o Formal abstractions and other complexity reduction techniques

Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Folsom

Additional Locations:

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $105,650.00-200,340.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.