Digital Verification Intern

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Digital Verification Intern

Location: Warszawa, Poland

Reports to: Design Engineering Architect

Job Overview:

If you are looking to gain your first hands‑on experience in SoC (System‑on‑Chip) design and verification, we invite you to join our team as a Digital Verification Intern.

In this role, you will work alongside experienced engineers and contribute to the creation of virtual components, from design specifications, through verification, to complex SoC designs.

This internship is designed to support learning, collaboration, and professional growth.

What you will do

• Support digital verification activities across different stages of the SoC development process.

• Learn how to translate design specifications into verification solutions.

• Contribute to verification environments under the guidance of experienced engineers.
• Develop your technical skills through practical, real‑world projects.

What we are looking for (essential)

• Currently studying towards, or recently completed, a BSc in Electronic Engineering, Micro‑Electronic Engineering, Computer Science, or a related field (including final‑year students).
• Basic understanding of digital electronics.
• Familiarity with Hardware Description Languages (HDL).
• Basic knowledge of object‑oriented programming (OOP) concepts.
• Ability to work in English (written and spoken).

Nice to have (but not required)

• Exposure to digital design concepts
• Awareness of verification methodologies such as OVM or UVM, SystemVerilog Assertions (SVA), or formal verification
• Experience with Python, Tcl/Tk, or other scripting languages

If you do not meet all the “nice to have” criteria, we still encourage you to apply.

What we offer

• Flexible working hours, supporting the combination of studies and practical experience
• Opportunity to complete a BSc or MSc thesis/project with Cadence
• Competitive salary package, aligned with skills and experience, based on internship or civil agreements
• Potential transition to a regular employment contract based on performance
• Mentorship and guidance from experienced managers and engineers
• Continuous learning through training sessions and seminars
• Collaboration with colleagues from international teams
• Multisport cards
• Social Fund benefits
• A supportive and inclusive work environment

We welcome candidates from diverse backgrounds and learning paths. If you are curious, motivated, and eager to grow in digital verification, we would be glad to hear from you.

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. 

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