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Candidate would be required to work on Design Implementation activities related to complex digital and mixed signal IP blocks used in the development of Broadcom’s ASIC / SoC products. Activities include constraints development, constraints verification, deployment of SDF, extracted timing models and timing closure. Additionally, the candidate could be required to do block-level synthesis, verification (static, formal) and place and route related activities. Candidate will work closely with the IP and SOC design teams to enable block and ASIC level timing closure.
Requirements:
Education and Experience required:
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $120,000 - $192,000.
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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