Design Engineer II (SoC/Systems Design)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title:   Design Engineer II

Location:   Edinburgh, United Kingdom

Reports to:   Design Engineering Architect

Job Overview:

The Cadence Computer Systems Group (CSG) develops Chiplet technology. This includes the Architecture of complex systems, integrating CPUs and high-performance DSPs, DDR and IO controllers, hardware accelerators, and subsystems. Our Chiplet designs are targeted towards most of the top semiconductor vendors today,  and we plan to scale  the Chiplet business significantly in the coming years.

The CSG Front end Chiplets Engineering team seeks an experienced and talented SoC/Systems design engineer to join a new team for CSG systems. In this role, you will be responsible for developing and validating reference systems for Computer Vision, Machine Learning, Radar, Automotive, and other high-performance applications.

This is a technically rewarding role with high visibility within the organization. The team is responsible for supporting customers of CSG subsystems. The group will also implement reference designs on emulation systems and support applications for product demonstrations.

This role requires prior experience primarily in RTL design, with knowledge in verification space an advantage. You will work closely with compute and interface IP development engineering, and 3rd party vendors, to build designs to demonstrate the capabilities of CSG Chiplet framework.

Responsibilities:

• Develop, implement, and debug SoC/Chiplet reference systems.
• Integrate compute, memory and interface IP in system designs.
• Analyse IP products and implementation flows.
• Identify gaps and work with development teams to improve products.
• Develop collateral, and training material for CSG system customers.
• Identify and implement best practices in hardware design, testing, and validation to improve efficiency and reliability.
• Stay up to date with latest industry trends, technologies, and design methodologies, and incorporate them into team’s workflows.

Requirements:

• BS in Electronic Engineering/Computer Science with 3+ years work experience, or MSc in EE/C.
• Must have experience in RTL design, including micro-architecture definition of digital portions of IP blocks, or verification. Demonstrated experience in any of the following areas:
  • Design of digital circuits and components using Verilog/System Verilog
  • Debugging in digital simulation environment
  • Multi-clock domain designs
  • Logic synthesis
  • FPGA implementation
• Experience with EDA tools like Cadence and Synopsys for design simulation and verification.

Check what we can offer you:

• Competitive salary
• 25 days holiday per year
• Private Medical and Dental plans, Income Protection and Life Insurance
• Group Personal Pension Plan
• Cycle to work scheme and gym subsidy
• 5 days paid time to volunteer to give back to our communities
• Employee Stock Purchase Plan
• The opportunity to work for a Great Place to Work© & Fortune 100 organization

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. 

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