Job Details:
Job Description:
You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems. Your responsibilities will include but not limited to:
1. Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.
2. In depth understanding of different memory design concepts ((SRAM/RF/ROM).
3. Expertise in Static timing analysis concepts.
4. Close work with Layout and Floor planning teams.
5. Back-end design implementation of new features.
6. Expertise in Memory post silicon analysis.
7. Good understanding of statistical variation.
Qualifications:
You must possess a Masters Degree in Electrical or Computer Engineering with atleast 8 or more years of experience in related field or a Bachelors Degree with atleast 10 years of experience. Technical Expertise in synthesis, P and R tools preferred.
Preferred Qualifications:
1. Digital Design Experience, with High Speed, Low Power.
2. Familiarity with Verilog.
3. Tcl, Perl, Python scripting.
4. Good understanding of spice simulations and analysis
5. Strong verbal and written communication skills.
Job Type:
Experienced Hire
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Business group:
The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.