Senior Design Verification Engineer

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

          

The ADI ADC team is seeking a motivated and experienced design verification engineer to provide support to our ADG BU located at ADI’s Valencia, Spain. As a Senior Design Verification Engineer, you will play a key role in defining and driving the verification strategy, planning, and execution. You will be part of a highly skilled team that develops verification environments and re-usable components using System Verilog and UVM.  At the block level and system level, you will be creating verification plans, developing and debugging tests, and using a metric driven methodology to evaluate results, including the monitoring of regressions, assertion coverage, code coverage and functional coverage. In addition, you will be investigating and driving the adoption of evolving new verification methodologies to handle the complex needs of these projects.

Responsibilities include, but not limited to:

• Plan, develop, document, and execute verification plans across multiple platforms, including simulation and emulation.
• Build and enhance SystemVerilog UVM-based simulation environments, infrastructure, and verification flows at block, subsystem, and full-chip levels.
• Develop, simulate, and debug both constrained-random and directed test cases aligned with verification plans.
• Define and implement functional coverage models, assertions, and metrics to measure verification progress and closure.
• Drive verification reviews, analyze coverage results, and implement actions to close gaps and ensure completeness.
• Evaluate and unify different verification methodologies while continuously improving productivity and efficiency.
• Collaborate with global verification teams to integrate internal and third-party IP/VIP into the verification environment.
• Partner with cross-functional teams (design, architecture, software, implementation) to ensure robust design quality and timely project execution.

Job qualifications

• Master’s degree in Computer/Electrical engineering or related field with strong background in digital design and design verification
• Experience with object-oriented programming, Systemverilog/UVM, Python, Perl
• Experience with Cadence, Synopsys, and/or Mentor tools for simulation
• Experience with System and Digital modeling languages (MATLAB or SystemC)
• Overall exposure to the design/verification tape-out cycle is desirable
• Prior experience working with multi-site teams and 3rd party VIP will be valuable

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

          

Required Travel: Yes, 10% of the time

          

Shift Type: 1st Shift/Days