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Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and has a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.
Who We Are
The Silicon Engineering Group is responsible for delivering Server and Client SoC designs and solutions such as Pre and Post Silicon System Validation Engineers. The role involves defining, developing, and executing SoC level power, thermal, and performance validation and optimization plans across Intel products. It requires an understanding of the business implications of maintaining power and performance KPIs within targets and adhering to power and thermal specifications.
Who You Are
We are looking for a highly motivated and technically savvy experienced engineer.
Responsibilities may include but are not limited to:
Ratifies optimizations from hardware/software architecture and proposes solutions to software PTP teams.
Develops power, thermal, and performance validation methodologies, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis.
Performs SoC level debug to identify root causes and resolve all functional and triage failures for power, thermal, and performance issues.
Develops validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing.
Configures and sets up data logger for thermal data collection and analysis.
Publishes SoC level power, thermal, and performance validation reports summarizing all validation and optimization activities performed, reviews results, and communicates to relevant teams.
Works with architecture, design, verification, firmware, software, and platform teams to maintain and improve debug, validation test strategy, methodologies, and processes to ensure power, thermal, and performance meet and exceed product completive targets and specifications.
Strong background in power/performance KPI development and optimization.
Debugging experience for SoC-level power, thermal, and performance failures.
Familiarity with validation tools such as data loggers, behavioral checkers, and state space coverage techniques.
Knowledge of hardware/software optimizations for power and performance.
Familiar with system board design/debugging and usage of lab equipment like Oscilloscope and Logic analyzer.
Experience of silicon verification, test program development and test plan execution.
Strong analytical and problem-solving abilities.
Effective communication and documentation skills for cross-functional collaboration.
Ability to work with architecture, design, verification, firmware, software, and platform teams
Knowledge of AI accelerators systems including GFX, NPU, NPP design and architecture.
Knowledge MIPI MPHY, JTAG, DDR, PCIe/USB/PCI-E/ETHERNET/SPMI bus protocol.
Knowledge of RTL language, in-circuit emulation and FPGA fast prototyping are an advantage.
Knowledge of validation tools such as data loggers, behavioral checkers, and state space coverage techniques.
Knowledge of hardware/software optimizations for power and performance.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelor's Degree in Electrical Engineering, Computer Engineering or similar field with 3+ years' of relevant experience -OR- Master’s Degree in Electrical Engineering, Computer Engineering or similar field with 2+ years of relevant experience
2+ years of experience in SoC FPGA/Emulation function.
2+ years of experience in Pre-Si functional design, validation, and/or HW/FW/SW integration.
2+ years of experience on major Pre-Si platforms: logic simulation or virtual platform or FPGA, and/or emulation.
2+ years of experience of C/C++, Python Programming language
2+ years of experience in debugging for SoC-level power, thermal, and performance failures.
Preferred Qualifications
Experience with System (SoC) level debug using JTAG debuggers.
Expertise in system-level power management of real-time processors and systems.
Experience with performance modeling, benchmarking, and validation infrastructure setup.
Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003
Annual Salary Range for jobs which could be performed in the US:
$121,050.00-197,230.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.