Director - IC Design(Front End)

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

Role Overview

The RTL Design Director leads the front-end design organization responsible for specification, RTL development, and delivery of high-quality, verified RTL and associated collateral for multiple SoCs. The role requires a deep understanding of digital design, SoC integration, architecture, and verification practices, combined with strong technical leadership and program management skills to deliver on schedule, power, performance, and area (PPA) targets.

Key Responsibilities

Strategic Leadership

• Define and execute the RTL design strategy and roadmap aligned with SoC and product requirements.
• ·Partner with SoC architects, verification, physical design, and firmware teams to ensure seamless integration and first-time-right silicon.
• Drive methodology, tool, and flow improvements across RTL development, linting, CDC, synthesis readiness, and power analysis.
• Build and mentor a high-performing global RTL design team, fostering technical excellence and collaboration.

Technical Execution

• Own RTL development for complex SoCs — from block design through SoC integration.
• Ensure high-quality deliverables through design reviews, coding standards, and rigorous sign-off criteria (lint, CDC, DFT readiness, coverage closure).
• Collaborate with architecture and verification teams to interpret specifications, drive micro-architecture decisions, and resolve functional issues.
• Oversee IP integration, interface definition, and interconnect design for multi-subsystem SoCs.
• Ensure deliverables meet timing, area, power, and functional goals through tight collaboration with physical design and STA teams.
• Lead the generation of SoC-level collateral — integration guidelines, configuration files, simulation models, and documentation.

Program and Cross-Functional Management

• Manage multiple SoC programs simultaneously, balancing resource allocation, risk, and delivery schedules.
• Interface with program management to track milestones and mitigate schedule or technical risks.
• Coordinate across global design centers to ensure design consistency, reuse, and alignment with corporate design methodology.
• Represent RTL design organization in design reviews, customer engagements, and executive updates.

Qualifications & Experience

• 15+ years of experience in digital design and SoC development, with at least 5 years in leadership/director capacity.
• Proven track record of leading RTL design teams delivering complex, multi-million gate SoCs to silicon.
• Strong experience with ARM-based subsystems, bus architectures (AMBA, AXI, ACE, etc.), and low-power design techniques.
• Exposure to front-end EDA tools (Synopsys, Cadence, Siemens) for lint, CDC, synthesis, and simulation.
• Hands-on familiarity with modern verification environments (UVM, constrained random, formal).
• Experience with cross-site teams and distributed design execution.

Education

• B.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, or Computer Engineering.
• Key Competencies
• Deep technical acumen in digital design and SoC architecture.
• Excellent leadership, mentoring, and communication skills.
• Strong organizational and program management abilities.
• Strategic thinker with a bias for execution and collaboration.

Success Metrics

• On-time delivery of high-quality RTL for multiple SoCs.
• Achievement of first-silicon success.
• Reduction in design cycle time via methodology and automation improvements.
• Team development, retention, and technical depth growth

Benefits & Perks

At Silicon Labs, you’ll be part of a highly skilled team where every engineer makes a meaningful impact. We promote work-life balance and a welcoming, fun environment.

• Equity Rewards (RSUs)

• Employee Stock Purchase Plan (ESPP)

• Insurance plans with outpatient cover

• National Pension Scheme (NPS)

• Flexible work policy

• Childcare support

Silicon Labs is an equal opportunity employer and values the diversity of our employees. Employment decisions are made on the basis of qualifications and job-related criteria without regard to race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status, or any other characteristic protected by applicable law.